diff --git a/crates/oxc_lexer/src/pipeline/coalesce/mod.rs b/crates/oxc_lexer/src/pipeline/coalesce/mod.rs
index e02da0f6ad..3fb21bb2d7 100644
--- a/crates/oxc_lexer/src/pipeline/coalesce/mod.rs
+++ b/crates/oxc_lexer/src/pipeline/coalesce/mod.rs
@@ -1,8 +1,9 @@
 use std::{ptr, slice};
 
 use crate::{
-    cpu::{Cpu, cpu_multiversion, cpu_select},
+    cpu::{Cpu, cpu_multiversion},
     error::DiagCode,
+    simd::prefetch,
     token::{TokenKind, tk},
 };
 
@@ -381,19 +382,3 @@ unsafe fn munch_walk(
     }
     pos
 }
-
-#[cpu_multiversion]
-#[inline(always)]
-fn prefetch(p: *const u8, cpu: impl Cpu) {
-    let _ = p; // Avoid clippy unused vars warning
-
-    cpu_select!(cpu, {
-        Avx2(_) => {
-            use std::arch::x86_64;
-            // SAFETY: `Avx2` type guarantees CPU supports AVX2
-            unsafe { x86_64::_mm_prefetch(p as *const i8, x86_64::_MM_HINT_T0) }
-        }
-        Neon(_) => { /* no-op */ }
-        Generic(_) => { /* no-op */ }
-    });
-}
diff --git a/crates/oxc_lexer/src/simd/mod.rs b/crates/oxc_lexer/src/simd/mod.rs
index ff07d032b2..e4b2132498 100644
--- a/crates/oxc_lexer/src/simd/mod.rs
+++ b/crates/oxc_lexer/src/simd/mod.rs
@@ -22,6 +22,7 @@
 //! - `data` has [`VecData128`] and [`VecData256`], aligned byte arrays to read into vectors.
 //! - `arrays` has traits for arrays of integers which vectors can read without alignment.
 //! - `operand` has traits which let an operation take either a vector or a scalar.
+//! - `prefetch` has a function which asks the CPU to fetch memory into the cache.
 //!
 //! [`cpu_impl`]: crate::cpu::cpu_impl
 
@@ -32,10 +33,12 @@ mod avx2;
 mod data;
 mod neon;
 mod operand;
+mod prefetch;
 mod vec128;
 mod vec256;
 
 pub use data::{VecData128, VecData256};
+pub use prefetch::prefetch;
 pub use vec128::Vec128;
 pub use vec256::Vec256;
 
diff --git a/crates/oxc_lexer/src/simd/prefetch.rs b/crates/oxc_lexer/src/simd/prefetch.rs
new file mode 100644
index 0000000000..b5ccc7e8a1
--- /dev/null
+++ b/crates/oxc_lexer/src/simd/prefetch.rs
@@ -0,0 +1,30 @@
+//! Prefetching memory into the cache.
+
+#[cfg(target_arch = "x86_64")]
+use std::arch::x86_64::{_MM_HINT_T0, _mm_prefetch};
+
+use crate::cpu::{Cpu, cpu_multiversion, cpu_select};
+
+/// Ask the CPU to fetch the cache line containing `p` into all levels of the cache.
+///
+/// Only a hint. Only AVX2 has an implementation. On other CPUs, it does nothing.
+#[cpu_multiversion]
+#[expect(clippy::inline_always)]
+#[inline(always)]
+pub fn prefetch(p: *const u8, cpu: impl Cpu) {
+    let _ = p; // Avoid clippy unused vars warning
+
+    cpu_select!(cpu, {
+        Avx2(_) => {
+            cfg_select! {
+                target_arch = "x86_64" => {
+                    // SAFETY: `Avx2` type guarantees CPU supports AVX2
+                    unsafe { _mm_prefetch(p.cast::<i8>(), _MM_HINT_T0) }
+                }
+                _ => {}
+            }
+        }
+        Neon(_) => { /* no-op */ }
+        Generic(_) => { /* no-op */ }
+    });
+}