fix(lexer): prevent dead code warnings when compiling crate for WASM (#28775)

Fix `dead_code` warnings when compiling `oxc_lexer` for WASM, which were introduced by #28772 and earlier PRs.

crates/oxc_lexer/src/simd/arrays.rs

@@ -23,6 +23,7 @@ pub unsafe trait IntArray64 {
     /// Get a `*const u8` pointing to start of the array.
     ///
     /// This pointer is guaranteed to be valid for unaligned reads of 8 bytes.
+    #[cfg_attr(not(any(target_arch = "x86_64", target_arch = "aarch64")), expect(dead_code))]
     #[expect(clippy::inline_always, reason = "no-op at runtime")]
     #[inline(always)]
     fn as_ptr(&self) -> *const u8 {
@@ -39,6 +40,7 @@ pub unsafe trait IntArray128 {
     /// Get a `*const u8` pointing to start of the array.
     ///
     /// This pointer is guaranteed to be valid for unaligned reads of 16 bytes.
+    #[cfg_attr(not(any(test, target_arch = "x86_64", target_arch = "aarch64")), expect(dead_code))]
     #[expect(clippy::inline_always, reason = "no-op at runtime")]
     #[inline(always)]
     fn as_ptr(&self) -> *const u8 {
@@ -55,6 +57,7 @@ pub unsafe trait IntArray256 {
     /// Get a `*const u8` pointing to start of the array.
     ///
     /// This pointer is guaranteed to be valid for unaligned reads of 32 bytes.
+    #[cfg_attr(not(any(test, target_arch = "x86_64", target_arch = "aarch64")), expect(dead_code))]
     #[expect(clippy::inline_always, reason = "no-op at runtime")]
     #[inline(always)]
     fn as_ptr(&self) -> *const u8 {

crates/oxc_lexer/src/simd/data.rs

@@ -94,6 +94,7 @@ impl VecData128 {
     /// Get a `*const u8` pointing to start of the array.
     ///
     /// This pointer is guaranteed to be valid for aligned reads of 16 bytes.
+    #[cfg_attr(not(any(test, target_arch = "x86_64", target_arch = "aarch64")), expect(dead_code))]
     #[inline(always)]
     pub const fn as_ptr(&self) -> *const u8 {
         self.0.as_slice().as_ptr()
@@ -102,6 +103,7 @@ impl VecData128 {
     /// Get a `*mut u8` pointing to start of the array.
     ///
     /// This pointer is guaranteed to be valid for aligned writes of 16 bytes.
+    #[cfg_attr(not(any(test, target_arch = "x86_64", target_arch = "aarch64")), expect(dead_code))]
     #[inline(always)]
     pub const fn as_mut_ptr(&mut self) -> *mut u8 {
         self.0.as_mut_ptr()
@@ -210,6 +212,7 @@ impl VecData256 {
     /// Get a `*const u8` pointing to start of the array.
     ///
     /// This pointer is guaranteed to be valid for aligned reads of 32 bytes.
+    #[cfg_attr(not(any(test, target_arch = "x86_64", target_arch = "aarch64")), expect(dead_code))]
     #[inline(always)]
     pub const fn as_ptr(&self) -> *const u8 {
         self.0.as_slice().as_ptr()
@@ -218,6 +221,7 @@ impl VecData256 {
     /// Get a `*mut u8` pointing to start of the array.
     ///
     /// This pointer is guaranteed to be valid for aligned writes of 32 bytes.
+    #[cfg_attr(not(any(test, target_arch = "x86_64", target_arch = "aarch64")), expect(dead_code))]
     #[inline(always)]
     pub const fn as_mut_ptr(&mut self) -> *mut u8 {
         self.0.as_mut_ptr()

crates/oxc_lexer/src/simd/operand.rs

@@ -22,6 +22,7 @@ use super::{CpuSimd, Vec128, Vec128Impl, Vec256, Vec256Impl};
 /// `C` is the CPU feature set of the [`Vec128`].
 pub trait Operand128<T, C: CpuSimd> {
     /// Convert to a [`Vec128`].
+    #[cfg_attr(not(any(test, target_arch = "x86_64", target_arch = "aarch64")), expect(dead_code))]
     fn into_vec128(self, cpu: C) -> Vec128<C>;
 }
 
@@ -74,6 +75,7 @@ where
 /// `C` is the CPU feature set of the [`Vec256`].
 pub trait Operand256<T, C: CpuSimd> {
     /// Convert to a [`Vec256`].
+    #[cfg_attr(not(any(target_arch = "x86_64", target_arch = "aarch64")), expect(dead_code))]
     fn into_vec256(self, cpu: C) -> Vec256<C>;
 }
 

crates/oxc_lexer/src/simd/vec128.rs

@@ -25,6 +25,7 @@ use super::{
 ///
 /// The methods which every CPU type has are in [`Vec128Impl`], and are also inherent methods.
 /// The `avx2` and `neon` modules have the methods which only one CPU type has.
+#[cfg_attr(not(any(target_arch = "x86_64", target_arch = "aarch64")), expect(dead_code))]
 pub struct Vec128<C: CpuSimd> {
     pub(super) inner: <C::Vec128 as Vec128Impl>::Inner,
     pub(super) cpu: C,
@@ -264,12 +265,14 @@ where
     }
 
     /// Create a [`Vec128`] by repeating `n` 16 times.
+    #[cfg_attr(not(any(test, target_arch = "x86_64", target_arch = "aarch64")), expect(dead_code))]
     #[inline(always)]
     pub fn splat(n: u8, cpu: C) -> Self {
         <Self as Vec128Impl>::splat(n, cpu)
     }
 
     /// Create a [`Vec128`] by repeating `n` 4 times.
+    #[cfg_attr(not(any(test, target_arch = "x86_64", target_arch = "aarch64")), expect(dead_code))]
     #[inline(always)]
     pub fn splat_u32(n: u32, cpu: C) -> Self {
         <Self as Vec128Impl>::splat_u32(n, cpu)
@@ -398,6 +401,7 @@ where
     // ----------------------------------------
 
     /// Check if all the bits of this [`Vec128`] are zero.
+    #[cfg_attr(not(any(test, target_arch = "x86_64", target_arch = "aarch64")), expect(dead_code))]
     #[inline(always)]
     pub fn is_zero(self) -> bool {
         <Self as Vec128Impl>::is_zero(self)
@@ -492,6 +496,7 @@ where
     /// `other` is either an `i8`, or another [`Vec128`] to compare byte by byte.
     ///
     /// Each byte of the result is `0xFF` if the byte in `self` is greater, otherwise `0x00`.
+    #[cfg_attr(not(any(test, target_arch = "x86_64", target_arch = "aarch64")), expect(dead_code))]
     #[inline(always)]
     pub fn gt_i8(self, other: impl Operand128<i8, C>) -> Self {
         <Self as Vec128Impl>::gt_i8(self, other)

crates/oxc_lexer/src/simd/vec256.rs

@@ -21,6 +21,7 @@ use super::{CpuSimd, Vec128, VecData256, arrays::IntArray256, operand::Operand25
 ///
 /// The methods which every CPU type has are in [`Vec256Impl`], and are also inherent methods.
 /// The `avx2` and `neon` modules have the methods which only one CPU type has.
+#[cfg_attr(not(any(target_arch = "x86_64", target_arch = "aarch64")), expect(dead_code))]
 pub struct Vec256<C: CpuSimd> {
     pub(super) inner: <C::Vec256 as Vec256Impl>::Inner,
     pub(super) cpu: C,
@@ -266,6 +267,7 @@ where
     }
 
     /// Create a [`Vec256`] by repeating `n` 32 times.
+    #[cfg_attr(not(any(test, target_arch = "x86_64", target_arch = "aarch64")), expect(dead_code))]
     #[inline(always)]
     pub fn splat(n: u8, cpu: C) -> Self {
         <Self as Vec256Impl>::splat(n, cpu)